In its first iteration, the Xccela Bus is a high-speed, high-performance Octal SPI bus that uses eight data lines for command and data transfer. It is fully compliant with the JEDEC xSPI standard.  The bus is synchronous and supports both single-data rate (SDR) operation, where one byte of data is transferred every clock cycle, and dual-data rate (DDR) operation in which two bytes of

data are transferred every clock cycle. The DDR operation requires the use of a data strobe signal (DQS). The Xccela Bus supports clock frequencies up to 200MHz and data transfer rates up to 400MB/sec (3.2Gbps).

Xccela™ Bus Specification (v1.0) Physical Layer Highlights

  • JEDEC xSPI standard compliant
  • SPI-compatible Xccela Bus interface Octal DDR protocol
    • Extended-SPI protocol with octal commands
    • Legacy SPI protocol
  • Single Data Rate (SDR) and Double Data Rate (DDR)
    • Data strobe (DQS) for DDR mode
  • Max clock frequency
    • 166MHz in SDR mode (166MB/sec. read)
    • 200MHz in DDR mode (400MB/sec. read)
  • Low active signal count
    • 10 pins for SDR and 11 pins for DDR
  • Single supply voltage (1.8V or 3.0V nominal)


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